Section: New Results

Green computing on SoC

Correct and Energy-Efficient Design of a Multimedia Application on SoC

We studied the design and analysis of multimedia applications such as the JPEG encoder on multiprocessor architectures [55] [24] [13] . A model-based approach was adopted by using the UML Marte specifications [54] . An abstract clock analysis has been proposed to deal with the correctness of system behaviors and to find the most suitable execution platform configurations regarding performance and energy consumption. Our approach offers a rapid and reliable design space analysis, which is crucial when implementing complex systems [37] .

Design Space Exploration for Efficient Data Intensive Computing on SoCs

Finding efficient implementations of data intensive applications, such as radar/sonar signal and image processing, on a system-on-chip is a very challenging problem due to increasing complexity and performance requirements of such applications. One major issue is the optimization of data transfer and storage micro-architecture, which is crucial in this context. We proposed a comprehensive method to explore the mapping of high-level representations of applications into a customizable hardware accelerator [52] . The high-level representation is given in a language named Array-OL. The customizable architecture uses FIFO queues and a double buffering mechanism to mask the latency of data transfers and external memory access. The mapping of a high-level representation onto a given architecture is achieved by applying loop transformations in Array-OL. A method based on integer partition is used to reduce the space of explored solutions. Our proposition aims at facilitating the inference of adequate hardware realizations for data intensive applications. It is illustrated on a case study consisting in implementing a hydrophone monitoring application.

Power Estimation

Within the context of the OPEN-PEOPLE project, we aim at addressing the power estimation challenges of embedded system design with a new approach, combining Functional Level Power Analysis with advanced SystemC – Transaction Level Modeling (TLM) simulation techniques, in order to formally prove qualitative and quantitative properties of the final system power estimation. This approach requires the construction of a power models from FLPA for different embedded boards (FPGA and ASIC) and building up system level simulation environment for the analysis of power model and proofs of properties of the simulated system [42] .

As a main contribution, we propose a new hybrid system-level power consumption estimation methodology for complex embedded systems [41] . A key word in our contribution is hybridization between abstraction levels. Almost all the previous studies focus on power estimation for a given abstraction level without overcoming the wall of speed/accuracy trade-off . The idea here is to build up a hybrid power estimation tool that combines Functional Level Power Analysis (FLPA) for hardware power modeling and Transactional Level Modeling (TLM) simulation technique for rapid system prototyping and fast power estimation. Basically, the FLPA is used for processor power modeling. In the frame of this work, it will be extended to cover the other hardware components used in the MultiProcessor System-on-Chip (MPSoC) such as the memory and the reconfigurable logic. After that, we go further in terms of scalability to target heterogeneous multiprocessor architectures. The functional power estimation part is coupled with a fast SystemC simulator in order to obtain the needed micro-architectural activities for power models, which allows us to reach a superior bargain between accuracy and speed[43] .